I. Field of the Invention
The present invention relates to Phase Locked Loops (PLL""s). More particularly, the present invention relates to a novel and improved method and apparatus for reducing the time required to obtain phase lock in a PLL that is activated following operation in standby mode.
II. Description of the Related Art
Accurate frequency sources are vital to the operation of numerous electronic systems and devices. Frequency sources are used as timing sources within electronic devices and are also used to tune electronic devices to desired communication channels.
Many types of accurate frequency sources are available. The specific type of frequency source implemented within a particular application is determined according to the design constraints of the particular application. Atomic docks exhibit extreme levels of frequency accuracy, however, their size, cost, and absence of tuning range greatly limit their actual application within an electronic system. Similarly, accurate frequency sources can be designed utilizing the piezoelectric effect of quartz crystals. The small size and relative accuracy of quartz crystal based frequency sources make them popular for most consumer based electronic devices. However, a frequency source based upon the fundamental frequency of a quartz crystal is limited by the minimal frequency tuning range and limitations on the fundamental frequency of a quartz crystal.
Indirect frequency synthesis is used to overcome the problems of the lack of frequency tuning and limited center frequency associated with fundamental quartz crystal frequency sources. Indirect frequency synthesis utilizes a Phase Locked Loop (PLL) to generate a frequency source that is a multiple of a reference frequency. Specific implementations of indirect frequency synthesis often use a quartz crystal oscillator as the reference frequency.
A frequency source implemented using indirect frequency synthesis is commonly known as a frequency synthesizer. A common implementation of a frequency synthesizer is shown in FIG. 1. A quartz crystal 20 is coupled to an oscillator 30 to generate a reference frequency. A reference divider 32 is coupled to the output of the oscillator 30 to scale the reference frequency. A Voltage Controlled Oscillator (VCO) 60 operates to provide the desired output of the frequency synthesizer 10. The output of the VCO 60 is also coupled to an output frequency divider 62 that generates a scaled output of the VCO 60. The output of the reference divider 32 is coupled to a first input of a phase detector 40. The output of the output frequency divider 62 is coupled to a second input of the phase detector 40. The phase detector 40 compares the scaled output from the output frequency divider 62 to the scaled output from the reference divider 32. The phase detector 40 output is a control signal based upon the comparison of the input signals. The phase detector 40 output is coupled to a loop filter 50 that limits the frequency component of the phase detector 40 output. The output of the loop filter 50 is coupled to a control input on the VCO 60. The signal on the control input of the VCO 60 operates to tune the VCO 60 output frequency. The frequency synthesizer 10 is thus a phase locked loop wherein the loop operates to maintain phase lock between the scaled reference frequency and the scaled output frequency. The common architecture of a frequency synthesizer 10 allows for a number of the functional blocks to be combined within a single Integrated Circuit (IC). A typical frequency synthesizer IC integrates the oscillator 30, reference divider 32, output frequency divider 62, and phase detector 40. The user is only required to provide the additional elements consisting of a crystal 20 for the oscillator 30, a VCO 60, and a loop filter 50 to complete the frequency synthesizer 10.
The operation of a Phase Locked Loop (PLL) is characterized by a number of parameters. These characteristics include the pull in time and pull in range. The pull in range is defined as the range of frequencies over which the PLL will acquire and lock the VCO output to the reference frequency. The pull in time represents the time required for the pull in process. Both the pull in range and pull in time are affected by the type of phase detector used in the PLL as well as the order of the loop filter.
The time the PLL takes to acquire and lock a VCO output signal is important in many applications. PLL lock time design constraints are determined by the specific application. Frequency synthesizers utilizing PLL""s are used within portable communication devices to generate Local Oscillator (LO) signals. LO signals are used to tune receivers and transmitters to specific channels. Typically, in a receiver the LO is used to downconvert the received RF signal to a baseband signal. Conversely, in a transmitter a LO is used to upconvert baseband signals to designated RF channels. Frequency synthesizers used for the generation of LO signals are found in devices such as two-way radios, stereo receivers, televisions, and wireless phones. However, one of ordinary skill in the art will recognize that frequency synthesizers are not limited to the generation of LO signals. Frequency synthesizers are capable of satisfying the requirements of the majority of frequency source applications.
Frequency synthesizer power consumption is an important design concern when the frequency synthesizer is used in a portable electronic device. The battery life on a portable electronic device decreases in proportion to increases in power consumption. Therefore, minimization of power consumption is highly desirable in electronic circuits used in portable electronic devices.
Portions of a wireless phone may be powered down under certain conditions in order to conserve battery power and extend battery life. In a wireless phone operating in a Code Division Multiple Access (CDMA) communication system, such as the one described in Telecommunications Industry Association (TIA)/Electronics Industries Association (EIA) 95-B MOBILE STATION-BASE STATION COMPATIBIY STANDARD FOR DUAL-MODE SPREAD SPECTRUM SYSTEMS, the phone may power down specific circuits under a variety of conditions. The system described by TIA/EIA 95-B allows the phone to operate at a reduced data rate during a phone call under certain conditions. When the phone is operating in the reduced data rate mode the phone""s transmitter transmits bursts of data packets. To conserve power, portions of the phone""s transmit chain are powered down during the time period in which the phone is not required to transmit any data.
Additional power savings are achieved by powering down portions of the phone during the time the phone is in the idle state where a call is not in progress. A CDMA phone operating in a TIA/EIA 95-B system performs a number of tasks while in the idle state. These tasks include performing registration procedures and idle handoff procedures. Additional tasks include receiving overhead messages, configuration messages, page messages, mobile station directed orders, data burst messages and acknowledgements for access channel messages. The phone is not continually active in the idle state. To take advantage of the limited phone activity in the idle state, portions of the phone can be powered down during periods within the idle state to further reduce power consumption and increase battery life. The phone can be placed in a standby or sleep mode during the idle state when no phone activity is required. Only critical portions of the phone remain powered up during sleep mode. All remaining noncritical portions of the phone are powered down to minimize phone power consumption. The frequency synthesizer used to generate the LO signals is one of the non-critical circuits powered down during the sleep mode.
However, the phone is periodically required to wake up and service the required idle state tasks. When the phone wakes up it is required to synchronize its timing with the system before it can transmit or receive communications. The time the phone uses to resynchronize with the system must be minimized in order to maximize the power savings gained by placing the phone in the sleep mode. The time required by the frequency synthesizer to tune and lock to the assigned frequency represent part of the phone synchronization time. Therefore, it is advantageous to minimize the time the frequency synthesizer uses to tune and lock to the desired frequency.
Standard methods of reducing the lock time of a PLL include increasing the VCO gain, increasing the bandwidth of the loop filter, and decreasing the damping factor of the loop filter. However, these lock time reduction methods are not available to the designer interested in reducing the PLL lock time for a frequency synthesizer that is switched from a sleep state to an idle mode in a wireless phone. This is because the performance of the frequency synthesizer in the locked state determines the majority of the parameters of the PLL. The values of VCO gain, loop filter bandwidth, and loop filter damping factor are limited by the design constraints imposed on the locked output of the frequency synthesizer. What is needed is a manner of improving the frequency synthesizer PLL lock time without degrading the performance of the frequency synthesizer output when the loop is locked.
The present invention is a novel and improved method and apparatus for decreasing the time required for a frequency synthesizer to lock after waking up from a sleep or standby mode. When the frequency synthesizer is placed in the sleep or standby mode the voltage on the VCO tuning line is maintained. The portions of the frequency synthesizer required to maintain phase lock are powered down during sleep mode to conserve power. The powered down circuits include the reference divider, phase detector, and output frequency divider. The voltage on the VCO tuning line is maintained at the voltage value that was on the VCO tuning line just prior to the frequency synthesizer being placed in the sleep mode.
In a frequency synthesizer Integrated Circuit (IC) the voltage at the VCO tune pin is maintained when the IC is placed in sleep mode. The IC samples the voltage value of the VCO control line just prior placing the IC in the sleep mode. The sampled value is maintained at the VCO tune pin of the frequency synthesizer IC.